module ledG_press_IO(
                input   wire            sclk,
                input   wire            input_active,
                input   wire            detect_sync,
                input   wire            sample_sync,
                
                input   wire            inner_led_g,                
                inout   tri             led_g,                                
                inout   tri             key_in,
                
                output  wire            press
                );

reg             detect_input;
reg     [1:0]   sample_period_count;
wire            ledG_press,key_press;

assign  led_g=(detect_input==0)? inner_led_g:1'bz;
assign  ledG_press=(detect_input==1 && sample_sync==1)? led_g:1'b1;

assign  key_in=(detect_input==0)?  inner_led_g:1'bz;                     
assign  key_press=(detect_input==1 && sample_sync==1)? key_in:1'b1;

assign  press=key_press & ledG_press;

always@(posedge sclk)
        if(detect_input==0)
                sample_period_count<=0;
        else if(sample_sync==1 && sample_period_count[1]==0)
                sample_period_count<=sample_period_count+1;

always@(posedge sclk)
        if(input_active==1)
                detect_input<=0;
        else begin
                if(detect_sync==1)                
                        detect_input<=1;
                else if(sample_sync==1 && sample_period_count[1]==1)
                        detect_input<=0;
                end

endmodule